Home > Embedded FPGA Development
Admin | Posted on 20/04/12
From the time Alan Turing came up with the idea of the Turing Machine, it has been mathematically proven that any calculation can be performed using a Turing Machine. Even with current-generation computers running at 3 GHz, certain calculations remain challenging to perform on time. This has driven advancements in Parallel Processing, Superscalar Processors, SMP (Symmetric Multi Processing), and Hyper-Threading. However, these solutions are limited by the types of problems they can address.
Problems need to be NC-hard to fully utilize hardware advantages. Moreover, communication between multiple processors for transferring values and making decisions can decrease overall processing speed, increase power requirements, and expand the required hardware size. A solution is the use of dedicated hardware for multiple calculations, such as MAC (Multiply and Accumulate) units, where VLIW instructions feed values for matrix multiplications in 3D geometry (rotation, translation). Intel popularized this as MMX, Apple as Altivec, and Texas Instruments DSPs also use similar techniques for faster number crunching.
For problems beyond NC and P-hard domains, customized hardware is needed to speed up computation, which general-purpose microprocessors and DSPs cannot provide. Additional challenges arise from I/O interfacing with newer sensors and devices, and from applications requiring multiple algorithms exchanging data while managing timing and synchronization. Large-scale systems may require connecting numerous devices efficiently.
FPGAs address these challenges by enabling parallel processing at very high speed, low power consumption, and customized hardware solutions. FPGAs can fulfill timing requirements and often provide a single-chip solution for applications interfacing multiple devices of various kinds.
Reshaping hardware with FPGAs provides advantages not possible with ASICs. The same chip can accommodate new devices not part of standard hardware. Hardware flexibility allows experimentation and optimization, such as adjusting buffer sizes or registers to suit new devices.
There are two common FPGA development approaches:
Both approaches allow parallelized calculations. The optimal approach depends on the developer’s requirements.
Processor-style FPGAs come in two forms:
FPGAs provide logic slices consisting of LUTs, multiplexers, flip-flops, DSP slices with multipliers, MACs, ALUs, SIMD units, and RAM to store essential functions like sine and cosine tables. They can be reprogrammed multiple times (e.g., SRAM-based FPGAs by Xilinx, Altera, Lattice) or be one-time programmable (e.g., Actel FPGAs).
The most common languages for FPGA programming are VHDL and Verilog. FPGA vendors provide tools for code simulation, floor planning, power optimization, and efficient I/O access.
Ascenten develops and verifies FPGA application modules based on customer requirements, often derived from algorithms or C code demonstrations. This reduces product development turnaround time and provides solutions where general-purpose processors are inadequate. Ascenten’s FPGA expertise supports low-power applications.
The company has experience with hard-core processor FPGAs (e.g., Xilinx Virtex with ML 403 PPC, Altera Cyclone V with ARM) and soft-core processor FPGAs (e.g., Spartan Microblaze, Altera Cyclone III & Stratix). In-house expertise in RTOS, Embedded Linux, and API development allows seamless integration of FPGA applications with PCs or LCD displays.
This article was also published on TechOnline: FPGA Development: A Blessing to the Embedded World
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